By Roopak Sinha, Parthasarathi Roop, Samik Basu

This ebook describes an procedure for designing Systems-on-Chip such that the approach meets specific mathematical necessities. The methodologies provided allow embedded platforms designers to reuse highbrow estate (IP) blocks from latest designs in an effective, trustworthy demeanour, instantly producing right SoCs from a number of, in all probability mismatching, components.

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Extra resources for Correct-by-Construction Approaches for SoC Design

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Any state formula is also a valid CTL formula. 3 presents visually how CTL formulae may be built by composing simpler formulae iteratively to construct more complex formulae. , state 1) is reached. The process starts in state 0 when any atomic proposition is selected and this automatically leads to a transition to state 1. Any time a temporal operator (X, F, G,U) prefixes a formula in state 1, a transition is made to state 2, since this creates a path formula. Only when a path formula (in state 2) is prefixed with a path quantifier, a transition is again made to state 1, since this leads to the creation of a state formula.

2 (Path). A path in a KS M starting from a state s is an infinite sequence of states π = so s1 s2 . .. such that (si , si+1 ) ∈ T holds for all i ≥ 0. We will use PATH(s) to denote the set of paths starting from state s in KS. 1 Model Checking 27 5 y, g 3 0 1 6 r, r r, g g, r y, y 2 7 4 g, y r, y y, r 8 Indicates ns light status Indicates ew light status g, g Fig. 2 Example: Model of a Traffic Light Controller We use a pedagogic example of a traffic light controller presented in [KG99] to motivate formal modelling.

These include symbolic techniques using BDD and SAT, abstraction based techniques such as refinement, and compositional verification techniques. A detailed discussion of these is beyond the scope of this text. 2 Module Checking • i=1: ( • i=2: 37 = ) ( = ) Iteration 2 : Formula EX(ew = g) 5 y, g 3 0 1 6 r, r r, g g, r EX(ew = g) (ew = g) (ew = g) EX(ew = g) y, y 7 2 4 g, y y, r r, y 8 Indicates ns light status Indicates ew light status g, g (ew = g) EX(ew = g) Fig. 2 Module Checking In the previous section, we considered the verification of closed systems.

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