By Aida Todri-Sanial, Jean Dijon, Antonio Maffucci

This e-book offers a single-source reference at the use of carbon nanotubes (CNTs) as interconnect fabric for horizontal, on-chip and 3D interconnects. The authors exhibit the makes use of of bundles of CNTs, as leading edge carrying out fabric to manufacture interconnect through-silicon vias (TSVs), so one can enhance the functionality, reliability and integration of 3D built-in circuits (ICs). This publication should be first to supply a coherent assessment of exploiting carbon nanotubes for 3D interconnects overlaying features from processing, modeling, simulation, characterization and purposes. insurance additionally incorporates a thorough presentation of the applying of CNTs as horizontal on-chip interconnects which could in all likelihood revolutionize the nanoelectronics undefined. This e-book is a must-read for someone drawn to the cutting-edge on exploiting carbon nanotubes for interconnects for either 2nd and 3D built-in circuits.

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Dennard R, Gaensslen F, Rideout V, Bassous E, LeBlanc A (1974) Design of ion-implanted MOSFETs with very small dimensions. IEEE J Solid-State Circuits 9:256–268 2. Buchanan D (1999) Scaling the gate dielectric: materials, integration and reliability. IBM J Res Dev 43:245–264 3. Yeo Y, Lu Q, Lee W, King T-J, Hu C, Wang X, Ma T (2000) Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric. IEEE Electron Device Lett 21:540–542 1 Overview of the Interconnect Problem 35 4.

3, the cell delay highly depends on the interconnect scenario at sub-11-nm technology nodes. 1 and 44 % at the 11- and 7nm technology nodes, respectively. This moderate change is due to the interconnects within the cell, which are short. 2 19 Experiment Setup and Results Having demonstrated the cell-level impact of the interconnect performance degradation with dimensional scaling, this section focuses on full-chip layout experiment results for three different categories of circuit blocks. These three different categories of circuits are represented by an encryption circuit (AES), a low-density parity check (LDPC) circuit, and a Fast Fourier Transform (FFT) circuit.

43. The inset figure shows the percentage variation in rc delay versus the variation in width as a percentage of the nominal width value for various interconnect pitches total wire area required for the nominal design and the worst case scenario for a 20 % variation in the wire width shows only a 4 % increase due to the variations. It is important to note here that there is a significant limitation that this methodology introduces and that is the number and pitch of each metal level are a free variable.

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