By Richard Munden
Richard Munden demonstrates how you can create and use simulation types for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf electronic elements. in response to the VHDL/VITAL common, those versions comprise timing constraints and propagation delays which are required for actual verification of today's electronic designs.
ASIC and FPGA Verification: A advisor to part Modeling expertly illustrates how ASICs and FPGAs may be proven within the higher context of a board or a procedure. it's a priceless source for any dressmaker who simulates multi-chip electronic designs.
*Provides a number of versions and a basically outlined technique for appearing board-level simulation.
*Covers the main points of modeling for verification of either common sense and timing.
*First publication to gather and train options for utilizing VHDL to version "off-the-shelf" or "IP" electronic parts to be used in FPGA and board-level layout verification.
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Additional resources for ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)
These pins are initialized to ‘W’ for reasons discussed in Chapter 16. 2 we have a model that would function correctly as a nand gate but has zero delay. All physical parts have some delay. Sometimes we rely on that delay, other times we would like it to go away, but we always have to account for it. So how do we add delays to our models? The simplest way of expressing a delay in VHDL is with an AFTER clause: YNeg <= A nand B AFTER 6 ns; This is fine if the part you are modeling happens to switch in 6 nanoseconds, in both directions, under all conditions.
ALL; where we call out a new library and package. The library, named FMF, is from the Free Model Foundry and the package is called gen_utils. The FMF library has several packages that are discussed in Chapter 3. The gen_utils package is used in this model to supply default values to some generics, as shown later. Lines 7 and 8, tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_B : VitalDelayType01 := VitalZeroDelay01; declare the tipd generics, which are the interconnect delays between components on the PCB (or between boards).
The gen_utils package is used in this model to supply default values to some generics, as shown later. Lines 7 and 8, tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_B : VitalDelayType01 := VitalZeroDelay01; declare the tipd generics, which are the interconnect delays between components on the PCB (or between boards). There should be one for each port of mode IN or INOUT in the port list. They are given default delay values of zero. Delay values for tipds must be nonnegative. For each port with an associated tipd we declare a signal to hold the delayed value of that port.