By Marvin Onabajo

This booklet describes a number of options to deal with variation-related layout demanding situations for analog blocks in mixed-signal systems-on-chip. The equipment offered are effects from fresh learn works concerning receiver front-end circuits, baseband clear out linearization, and information conversion. those circuit-level innovations are defined, with their relationships to rising system-level calibration ways, to song the performances of analog circuits with electronic tips or keep watch over. assurance additionally contains a technique to make the most of on-chip temperature sensors to degree the sign strength and linearity features of analog/RF circuits, as established by way of try out chip measurements.

  • Describes numerous variation-tolerant analog circuit layout examples, together with from RF front-ends, high-performance ADCs and baseband filters;
  • Includes integrated checking out strategies, associated with present commercial trends;
  • Balances digitally-assisted functionality tuning with analog functionality tuning and mismatch aid approaches;
  • Describes theoretical recommendations in addition to experimental effects for attempt chips designed with variation-aware techniques.

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Extra resources for Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip

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Such a test strategy would open doors for positive impact of the circuit-level adjustment features from this research on product yields. Since the suggested approach in [34] involves crude and fast tests around the acceptable minimum and maximum specification limits for a given parameter, digital programmability in the analog blocks makes retesting with fast on-chip performance tuning possible. Therefore, in reference to Fig. 1, self-calibration leads to narrower parameter distributions and thus higher production yields [34].

Additionally, the receiver path in [33] contains 8-bit current-steering DACs to cancel DC offsets at the output of the mixing stage. Digital correction of I/Q gain mismatches can also be carried out immediately after the down-conversion by generating the bias currents for the mixers in the I and Q paths with separate current sources consisting of multiple elements [36]. This is visualized for a single-balanced mixer in Fig. 9, where control bits B1–B0 set the conversion gain. Second-order nonlinearities due to mismatches in the mixer can be reduced as well with load resistors that are comprised of multiple parts and switches [36], which enables mismatch compensation by setting the optimum resistor value for each branch at the mixer output with digital control bits D1–DN.

This path contains the duplicate mixing operations as in the main path with the exception that the output signal at the second intermediate frequency (fIF2) can be of the form cos(2pÁfIF2Át) or sin(2pÁfIF2Át), depending on which phases of the two local oscillators (LO1, LO2) are routed to the auxiliary mixers. Finally, mixer3 correlates the signals from the two paths to extract the I/Q mismatch information contained in the DC component after the lowpass filter (LPF). g. 57 dB in [14]). A similar automatic IRR calibration with analog mixers, variable phase shifter, and gain tuning has been realized in [15] with an IRR of 59 dB.

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