By Alpha Architecture Committee, Richard T. Witek

This can be the authoritative reference on electronic apparatus Corporation's new 64-bit RISC Alpha structure. Written by way of the designers of the inner electronic necessities, this e-book includes whole descriptions of the typical structure required for all implementations and the interfaces required to aid the OSF/1 and OpenVMS working systems.

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If a b r a n c h is t a k e n b e t w e e n t h e LDx_L a n d t h e STx_C, t h e sequence above m a y always fail on some i m p l e m e n t a t i o n s ; hence, no useful p r o g r a m should do t h i s . ) • If a s u b s e t t e d instruction (for example, floating-point) is done b e t w e e n t h e LDx_L a n d t h e STx_C, t h e sequence above m a y always fail on some i m p l e m e n t a t i o n s , because of t h e Illegal I n s t r u c t i o n Trap; hence, no useful p r o g r a m should do t h i s .

It is a t least 8 ( m i n i m u m lock r a n g e is a n aligned quadword) a n d is a t most t h e page size for t h a t i m p l e m e n t a t i o n ( m a x i m u m lock r a n g e is one physical page). A processor's lock_flag is also cleared if t h a t processor e n c o u n t e r s a CALL_PAL R E I instruction. It is U N P R E D I C T A B L E w h e t h e r or not a processor's lock_flag is cleared on a n y o t h e r CALL_PAL instruction. It is U N P R E D I C T A B L E w h e t h e r a processor's lock_flag is cleared by t h a t processor's executing a n o r m a l load or store instruction.

Ab) ÎMemory format Operation: va <- {{Rbv + SEXT(disp)} AND NOT 7} (va)<63:0> «- Rav<63:0> Exceptions : Access Violation F a u l t on Write Translation N o t Valid Instruction mnemonics: STQ_U Store U n a l i g n e d Q u a d w o r d from Register to Memory Qualifiers: None Description: The v i r t u a l a d d r e s s is computed by a d d i n g register Rb to t h e sign-extended 16-bit displacement, t h e n clearing t h e low order t h r e e bits. T h e R a o p e r a n d is w r i t t e n to memory a t t h i s a d d r e s s .

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