By D. Crawley, K. Nikolic, M. Forshaw
It truly is changing into more and more transparent that the two-dimensional format of units on machine chips is beginning to prevent the advance of high-performance computers. three-d constructions should be had to give you the functionality required to enforce computationally in depth projects. three-D Nanoelectronic computing device structure and Implementation reports the cutting-edge in nanoelectronic equipment layout and fabrication and discusses the architectural elements of three-D designs, together with the potential use of molecular wiring and carbon nanotube interconnections. this can be a priceless reference for these eager about the layout and improvement of nanoelectronic units and know-how.
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Additional info for 3D Nanoelectronic Computer Architecture and Implementation (Series in Materials Science and Engineering)
Metallic connections may also be used and a number of different techniques have been developed. 5. Here, it is not possible to distinguish a vertical interconnection ‘layer’. Because the vertical connections are formed by metal deposition into deep trenches, they can be considered as extended vias which also connect the stacked chips. Another important distinction between this technique and those described earlier, is that fabrication of the stack must be done at the wafer level as opposed to assembling a stack from dice which have already been cut from their wafers because it is necessary to perform process steps such as etching and metallization.
5. Schematic cross-section view of a vertically integrated circuit, after . 6. Example of a stacked chip structure using capacitive vertical signal paths. because only working chips are used. When wafers are bonded together and later sawn into stacks, a stack may contain one or more faulty layers which, unless fault tolerant techniques are used, may cause the entire stack to fail. However, this may be of little significance where the yield of working chips is high and the number of layers in the stack is small.
Most of the motivation has previously come from a desire to reduce the physical size of systems, for example for aerospace applications, hearing aids or products such as Flash memory and mobile phones. It is also interesting to note that more work is being directed towards the development of CAD tools for the design of integrated circuits intended to be part of a 3D system. However, as discussed in chapter 1, it is only comparatively recently that the problems associated with wiring delays  have become sufficiently serious for more attention to be directed towards 3D systems.